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ADJD-S313-QR999 miniature surface-mount rgb digital color sensor data sheet description the ADJD-S313-QR999 is a cost effective, cmos digital output rgb color sensor in miniature surface-mount package with a mere size of 5x5x0.75mm. the ic comes with integrated rgb filters, an analog-to-digital converter and a digital core for communication and sensitivity control. the output allows direct interface to micro-controller or other logic control for further signal processing without the need of any additional components. this device is designed to cater for wide dynamic range of illumination level and is ideal for applications like portable or mobile devices which demand higher integration, smaller size and low power consumption. sensitivity control is performed by the serial interface and can be optimized individually for the different color channel. the sensor can also be used in conjunction with a white led for reflective color management. general specifications features ? fully integrated rgb digital color sensor ? digital i/o via 2-wire serial interface ? industrys smallest form factor C qfn 5x5x0.75mm ? adjustable sensitivity for different levels of illumination ? uniformly distributed rgb photodiode array ? 7 bit resolution per channel output ? built in internal oscillator ? sleep function when not in use ? no external components ? low supply voltage (v dd ) 2.6v ? 0 c to 70 c operating temperature ? lead free package applications ? general color detection and measurement ? mobile appliances such as mobile phones, pdas, mp3 players,etc. ? consumer appliances ? portable medical equipments ? portable color detector/reader feature value interface 100khz serial interface supply 2.6v digital (nominal), 2.6v analog (nominal) avago technologies' products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago technologies or its suppliers, for all loss, damage, expense or liability in connection with such use. esd warning: standard cmos handling precautions should be observed to avoid static discharge.
2 block diagram photocurrent to voltage conversion blue sdaslv sclslv xrst rgb photosensor array sleep gain selection control core photocurrent to voltage conversion red photocurrent to voltage conversion green analog to digital conversion powering the device 0v t vdd_ramp v ddd / v dda no voltage must be applied to io's during power-up and power-down ramp time esd protection diode turn-on during power-up and power-down a particular power-up and power-down sequence must be used to prevent any esd diode from turning on inadvertently. the figure above describes the sequence. in general, avdd and dvdd should power-up and powerdown together to prevent esd diodes from turning on inadvertently. during this period, no voltage should be applied to the ios for the same reason. ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential difference between agnd and dgnd may cause the esd diodes to turn on inadvertently.
3 electrical specifications absolute maximum ratings (notes 1 & 2) recommended operating conditions dc electrical specifications over recommended operating conditions (unless otherwise specified) ac electrical specifications parameter symbol conditions minimum ty p i cal (note 3) maximum units output voltage high level (note 5) v oh i oh = 3ma v ddd -0.8 v ddd -0.4 v output voltage low level (note 6) v ol i ol = 3ma 0.2 0.4 v dynamic supply current (note 7,8) i dd_dyn (note 9) 9.4 14 ma static supply current (note 8) i dd_static (note 9) 2.7 ma sleep-mode supply current (note 8) i dd_slp (note 9) 0.2 15 ua input leakage current i leak -10 10 ua parameter symbol minimum maximum units notes storage temperature t stg_abs -40 85 c digital supply voltage, dvdd to dvss v ddd_abs -0.5 3.7 v analog supply voltage, avdd to avss v dda_abs -0.5 3.7 v input voltage v in_abs -0.5 v ddd +0.5 v all i/o pins solder reflow peak temperature t l_abs 235 c human body model esd rating esd hbm_abs 2 kv all pins, human body model per jesd22-a114-b parameter symbol conditions minimum ty p i cal (note 3) maximum units internal clock frequency f clk 16 26 38 mhz parameter symbol minimum typical maximum units free air operating temperature t a 02570c digital supply voltage, dvdd to dvss v ddd 2.5 2.6 3.6 v analog supply voltage, avdd to avss v dda 2.5 2.6 3.6 v output current load high i oh 3ma output current load low i ol 3ma input voltage high level (note 4) v ih 0.7 v ddd v ddd v input voltage low level (note 4) v il 00.3 v ddd v
4 maximum sensitivity minimum sensitivity maximum sensitivity parameter symbol conditions minimum typ i cal (note 3) maximum units irradiance responsivity re p = 460 nm refer note 10 b 36 lsb / (mw/cm 2 ) p = 542 nm refer note 11 g 53 p = 645 nm refer note 12 r 82 parameter symbol conditions minimum typ i cal (note 3) maximum units irradiance responsivity re p = 460 nm refer note 10 b 1250 lsb / (mw/cm 2 ) p = 542 nm refer note 11 g 1750 p = 645 nm refer note 12 r 2490 parameter symbol conditions minimum ty p ic al (note 3) maximum units saturation irradiance (note 13) p = 460 nm refer note 10 b 4.17 mw/ cm 2 p = 542 nm refer note 11 g 2.83 p = 645 nm refer note 12 r 1.83 parameter symbol conditions minimum ty p ic al (note 3) maximum units saturation irradiance (note 13) p = 460 nm refer note 10 b 0.12 mw/ cm 2 p = 542 nm refer note 11 g 0.09 p = 645 nm refer note 12 r 0.06 minimum sensitivity optical specification *code is from dark code to (dark code + 128lsb) parameter symbol conditions minimum ty p i cal (note 3) maximum units dark offset* v d ee = 0 65 lsb
5 spectral response 0 0.2 0.4 0.6 0.8 1 400 500 600 700 wavelength (nm) relative sensitivity typical spectral response when the gains for all the color channels are set at equal. serial interface timing information figure 1. serial interface bus timing waveforms parameter symbol minimum maximum units scl clock frequency f scl 0 100 khz (repeated) start condition hold time t hd:sta 4 s data hold time t hd:dat 0 3.45 s scl clock low period t low 4.7 - s scl clock high period t high 4.0 - s repeated start condition setup time t su:sta 4.7 - s data setup time t su:dat 250 - ns stop condition setup time t su:sto 4.0 - s bus free time between start and stop conditions t buf 4.7 - s - notes: 1. the absolute maximum ratings are those values beyond which damage to the device may occur. the device should not be operated at these limits. the parametric values defined in the electrical specifications table are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will define the conditions for actual device operation. 2. unless otherwise specified, all voltages are referenced to ground. 3. specified at room temperature (25 c) and v ddd = v dda = 2.6v. 4. applies to all di pins. 5. applies to all do pins. sdaslv go tri-state when output logic high. minimum v oh depends on the pull-up resistor value. 6. applies to all do and dio pins. 7. dynamic testing is performed with the ic operating in a mode representative of typical operation. 8. refers to total device current consumption. 9. output and bidirectional pins are not loaded. 10. test condition is blue light of peak wavelength ( p ) 460 nm and spectral half width ( ? ?) 25 nm. 11. test condition is green light of peak wavelength ( p ) 542 nm and spectral half width ( ? ?) 35 nm 12. test condition is red light of peak wavelength ( p ) 645 nm and spectral half width ( ? ?) 20 nm 13. saturation irradiance = (msb)/(irradiance responsivity) sda scl t hd:sta t low t high t su:dat t hd:dat t su:sto t buf s ps t su:sta t hd:sta sr
6 high level description the sensor needs to be configured before it can be used. the gain selection needs to be set for optimum performance depending on light levels. the flowcharts below describe the different procedures required. sensor gain optimization flowchart sensor operation flowchart sensor gain optimization step 1 hardware reset step 2 device initialization step 3 - 4 select sensor gain settings step 5 acquire adc readings adc readings optimum? stop yes no sensor operation step 1 hardware reset step 2 device initialization step 3 - 4 select sensor gain settings step 5 acquire dark offset and store current offset values step 6 acquire adc readings step 7 compute sensor values stop * please refer to application note for more detailed information.
7 detail description a hardware reset (by asserting xrst) should be performed before starting any operation. the user controls and configures the device by programming a set of internal registers through a serial interface. at the start of application, the following setup data must be written to the setup registers: address (hex) register setup data (hex) 03 setup0 01 04 setup1 01 0c setup2 01 0d setup3 01 0e setup4 01 sensor gain settings the sensor gain can be adjusted by varying the photodiode size and integration time of the sensor manually through the following registers. sensor sensitivity ~ photodiode size x integration time slot setup value for photodiode size the following value can be written to each of the photodiode size registers to adjust the gain of the sensor. the default value after reset for these registers is 07h. setup value for integration time the following value can be written to each of the integration time registers to adjust the gain of the sensor. the default value after reset for these registers is 07h. sensor adc output registers to obtain sensor adc value, 02 hex must be written to acq register before reading the sensor adc output registers. address (hex) register description 02 acq acquire sensor analog to digital converter (adc) values when 02h is written. reset to 00h when sensor acquisition is completed 44 adcr sensor red channel adc value 43 adcg sensor green channel adc value 42 adcb sensor blue channel adc value value (hex) photodiode size 01 ? 03 ? 07 ? 0f full value (hex) integration time slot 00 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0a 11 0b 12 0c 13 0d 14 0e 15 0f 16 address (hex) register description 0b pdasr red channel photodiode size 0a pdasg green channel photodiode size 09 pdasb blue channel photodiode size 11 tintr red channel integration time 10 tintg green channel integration time 0f tintb blue channel integration time
8 serial interface reference description the programming interface to the adjd-s313 is a 2-wire serial bus. the bus consists of a serial clock (scl) and a serial data (sda) line. the sda line is bi-directional on adjd-s 313 and must be connected through a pull-up resistor to the positive power supply. when the bus is free, both lines are high. the 2-wire serial bus on adjd-s313 requires one device to act as a master while all other devices must be slaves. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. slaves are identified by unique device addresses. both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. a transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. the adjd-s313 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. figure 1. start/stop condition s start condition p stop condition sda scl start/stop condition the master initiates and terminates all serial data transfers. to begin a serial data transfer, the master must send a unique signal to the bus called a start condition. this is defined as a high to low transition on the sda line while scl is high. the master terminates the serial data transfer by sending another unique signal to the bus called a stop condition. this is defined as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condition. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are functionally identical. data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low. sda scl data valid data change figure 2. data bit transfer
9 the scl clock line synchronizes the serial data transmission on the sda data line. it is always generated by the master. the frequency of the scl clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. the master by default drives the sda data line. the slave drives the sda data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. the sda data line driven by the master may be implemented on the negative edge of the scl clock line. the master may sample data driven by the slave on the positive edge of the scl clock line. figure shows an example of a master implementation and how the scl clock line and sda data line can be synchronized. a complete data transfer is 8-bits long or 1-byte. each byte is sent most significant bit (msb) first followed by an acknowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes (depending on the data format). figure 3. data bit synchronization figure 4. data byte transfer figure 5. slave-receiver acknowledge acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave- receiver and master-transmitter, if the slave- receiver does not send an acknowledge bit, the master-transmitter can either stop the transfer or generate a repeated start to start a new transfer. sda scl sda data sampled on the positive edge of scl sda data driven on the negative edge of scl sda scl msb lsb 12 89 ack 12 8 9 no ack s or sr sr or p p sr start or repeated start condition stop or repeated start condition msb lsb scl (master) 8 9 sda (slave-receiver) sda (master-transmitter) lsb acknowledge acknowledge clock pulse sda left high by transmitter sda pulled low by receiver
10 addressing each slave device on the serial bus needs to have a unique address. this is the first byte that is sent by the master-transmitter after the start condition. the address is defined as the first seven bits of the first byte. the eighth bit or least significant bit (lsb) determines the direction of data transfer. a one in the lsb of the first byte indicates that the master will read data from the addressed slave (master- receiver and slave-transmitter). a zero in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the first byte and set itself up as a slave- transmitter or slave-receiver depending on the lsb of the first byte. the slave address on adjd-s313 is 0x58 (7-bits). in the case of the master-receiver and slave- transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the master can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. scl (master) 89 sda (slave-transmitter) sda (master-receiver) acknowledge clock pulse lsb sda left high by transmitter not acknowledge sda left high by receiver p sr stop or repeated start condition figure 6. master-receiver acknowledge msb lsb r/w a1 a6 a5 a4 a3 a2 a0 slave address 10 1 10 0 0 figure 7. slave addressing
11 a6 a5 a4 a3 a2 a1 a0 w a s a p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 master sends slave address master writes register address master writes register data master will write data start condition stop condition slave acknowledge a slave acknowledge slave acknowledge data format adjd-s313 uses a register-based programming architecture. each register has a unique address and controls a specific function inside the chip. to write to a register, the master first generates a start condition. then it sends the slave address for the device it wants to communicate with. the least significant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowledges, the master generates a stop condition to end the data transfer. figure 8. register byte write protocol a6 a5 a4 a3 a2 a1 a0 w a s d7 d6 d5 d4 d3 d2 d1 d0 master will write data start condition slave acknowledge a p d7 d6 d5 d4 d3 d2 d1 d0 stop condition a6 a5 a4 a3 a2 a1 a0 r sr master will read data repeated start condition slave acknowledge a master not acknowledge a slave acknowledge master sends slave address master writes register address master sends slave address master reads register data to read from a register, the master first generates a start condition. then it sends the slave address for the device it wants to communicate with. the least significant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least significant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then acknowledge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. figure 9. register byte read protocol
12 powering the device ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential difference between agnd and dgnd may cause the esd diodes to turn on inadvertently. pin information 15 avdd dgnd dvdd agnd xrst sdaslv sclslv voltage regulator voltage regulator host system xrst sda scl 10 12 11 19 8, 16, 17, 18 5, 6 7 star-connected ground sleep 10k host system 10k 10k 10k dvdd pin name type description 1 nc no connect no connect. leave floating. 2 nc no connect no connect. leave floating. 3 nc no connect no connect. leave floating. 4 nc no connect no connect. leave floating. 5 dgnd ground tie to digital ground. 6 dgnd ground tie to digital ground. 7 dvdd power digital power pin. 8 agnd ground tie to analog ground. 9 nc no connect no connect. leave floating. 10 xrst input global, asynchronous, active-low system reset. when asserted low, xrst resets all registers. minimum reset pulse low is 10 s and must be provided by external circuitry. 11 sclslv input sdaslv and sclslv are the serial interface communications pins. sdaslv is the bidirectional data pin and sclslv is the interface clock. a pull-up resistor should be tied to sdaslv because it goes tri-state to output logic 1. 12 sdaslv input/output (tri-state high) 13 nc no connect no connect. leave floating. 14 nc no connect no connect. leave floating. 15 sleep input when sleep=1, the device goes into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. 16 agnd ground tie to analog ground. 17 agnd ground tie to analog ground. 18 agnd ground tie to analog ground. 19 avdd power analog power pin. 20 nc no connect no connect. leave floating. application diagrams
13 package dimensions bottom view note: dimensions are in milimeters (mm)
14 recommended reflow profile it is recommended that henkel pb-free solder paste lf310 be used for soldering adjd-s313. below is the recommended soldering profile. 20 lead qfn recommended stencil design a stencil thickness of 2.18mm (6 mils) for this qfn package is recommended. 3.19 mm 3.19 mm 0.8 mm 0.4 mm 5.5 mm 5.5 mm 3.9 mm 2.18mm 0.8 mm 0.4 mm 20 lead qfn recommended pcb land pad design ipc-sm-782 is used as the standard for the pcb land pad design. recommended pcb finishing is gold plated. delta-flux = 2 c/sec. max. delta-cooling = 2 c/sec. max. t-min. t-max. t-reflow t-peak t-reflow t-pre 40-60 sec. max. 20-40 sec. max. 120 c 160 c 218 c 230 5 c time temperature delta-ramp = 1 c/sec. max.
15 package tape and reel dimensions carrier tape dimensions recommendations for handling and storage of adjd-s313 this product is qualified as moisture sensitive level 3 per jedec j-std-020. precautions when handling this moisture sensitive product is important to ensure the reliability of the product. do refer to avago application note an5305 handling of moisture sensitive surface mount devices for details. a. storage before use ? unopened moisture barrier bag (mbb) can be stored at 30c and 90%rh or less for maximum 1 year ? it is not recommended to open the mbb prior to assembly (e.g. for iqc) ? it should also be sealed with a moisture absorbent material (silica gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag b. control after opening the mbb ? the humidity indicator card (hic) shall be read immediately upon opening of mbb ? the components must be kept at <30c/60%rh at all time and all high temperature related process including soldering, curing or rework need to be completed within 168hrs c. control for unfinished reel ? for any unused components, they need to be stored in sealed mbb with desiccant or desiccator at <5%rh d. control of assembled boards ? if the pcb soldered with the components is to be subjected to other high temperature processes, the pcb need to be stored in sealed mbb with desiccant or desiccator at <5%rh to ensure no components have exceeded their floor life of 168hrs e. baking is required if: ? 10% or 15% hic indicator turns pink ? the components are exposed to condition of >30c/ 60%rh at any time. ? the components floor life exceeded 168hrs ? recommended baking condition (in component form): 125c for 24hrs k o b o section b-b section a-a a o 0.30 0.05 b b aa 1.75 0.10 5.50 0.05 12.00 0.10 r 0.50 typ. 1.55 0.05 8.00 0.10 1.50 (min.) 4.00 0.10 see note #2 2.00 0.05 see note #2 a o : b o : k o : pitch: width: 5.30 5.30 2.20 8.00 12.00 notes: 1. a o and b o measured at 0.3 mm above base of pocket. 2. 10 pitches cumulative tolerance is 0.2 mm. 3. dimensions are in millimeters (mm).
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countrie s. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes av01-0470en av01-0688en - january 4 , 2007 reel dimensions 18.0 max.* 178.0 0.5 12.4 45 45 65 r10.65 r5.2 +1.5* - 0.0 55.0 0.5 176.0 512 embossed ribs raised: 0.25 mm width: 1.25 mm back view notes: 1. *measured at hub area. 2. all flange edges to be rounded. avago technologies' products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago technologies or its suppliers, for all loss, damage, expense or liability in connection with such use. esd warning: standard cmos handling precautions should be observed to avoid static discharge.

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